CS552 Course Wiki: Spring 2021 | Synthesis »
Common Synthesis Errors and Synthesis FAQ |
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1. Can't find synth.pl
2. sh: dc_shell-t : command not found3. Cannot execute dc_shell-t. Something is wrong. Did you perform all the environment setup steps?
4. ERROR ./(filename).v is redefinedYou probably added a file twice in your list. Delete one of them. Run with -check again. This error you MUST fix. 5. Warning: Unable to resolve reference 'foo' in 'bar'6. Warning: Design 'xxx' has '4' unresolved references.This warning you MUST fix. This means you forgot to add the file foo.v to your file list. If you ignore this warning and continue with --cmd=synth, synthesis will *appear* to succeed. But if you look at the cell report you will see cell area zero against some cells. For example: mux2_1 0.000000 1 0.000000 b mux2_1_16bit_0 0.000000 1 0.000000 b, h mux2_1_16bit_1 0.000000 1 0.000000 b, h mux2_1_16bit_2 0.000000 1 0.000000 b, h mux4_1_16bit 0.000000 1 0.000000 b, h This is incomplete synthesis. 7. Error: Cannot find the specified driving cell in memory. (UID-993)8. Error: Could not read the following target libraries:9. Error: Cannot read file 'your_library.db'. (UID-58)
10. Can't find my error hereEmail the the Instructor and TA. Include the full text of the error and include your verilog file on which the warning or error was reported as an attachment in that email. |
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