Cache Simulator

Cache Simulator

cachesim is a cache simulator which simulates a cache based on its input parameters. It has four/five inputs:

1. Associativity: It defines cache associativity. For example, associativity is 1 for a direct-map cache or 2 for a 2-way set associativity cache.
2. Cache Size: It defines cache size in bytes. For example, for the direct-map cache designed in Hw 5, which has 256 sets of 4 16-byte words, the size is 2048.
3. Cache Block Size: It defines cache block size in bytes. For example, in Hw 5, each cache block is 4 2-byte words, therefore, cache block size is 8.
4. Trace Input File: It is a trace file which is used as input of cacheSim.
5. pseudoRandom: The fifth input, if present should be either pseudoRandom or pr. If specified, this option overrides the default LRU replacement algorithm and

uses pseudo random replacement instead.

For example to simulate the direct-map cache designed in HW5, you should use cachesim as follows:

cachesim 1 2048 8 mem1.addr

You can use any of test traces and assign its path as the last input parameter to cachesim.

To simulate 2-way set associative cache you have designed in Hw 5, you should use cachesim in this way:

cachesim 2 4096 8 mem_2way7.addr pseudoRandom

cachesim shows actions happening in the defined cache after running each line of the trace input file. Example running:

cachesim 1 2048 8 mem5.addr
output:
Load Miss for Address 348
Load Miss for Address 2396 with Eviction

Which are the actions happening when running mem5.addr (one load to 348 and one load to 2396)