Processor

Processor

• This describes the sequential logic and clocking methodology.
  • Single Cycle datapath and control are described.
  • Logic is combinational if output is a function of inputs. It is sequential if output is a function of past and current inputs.
• Processor Implementation
  • We describe 1 CPI datapaths using combinational logic building blocks of adder, ALU, MUX, register,register files and memory.
  • The datapath takes 1 CPI. For all instructions - Fetch, decode, execute, memory and writeback takes one cycle.
  • It is best to describe these stages here instead of just repeating stuff from Karu's slides.
  • Instruction Fetch
    • In this stage, the instruction to be executed next is fetched from memory using PC (program counter) as the address of the memory location. Corresponding location in the (instruction) memory is accessed and is assigned to the instruction register (IR).
    • IR <-- Mem[PC];
    • Next, the program counter is incremented to point to the next instruction. This is done by adding 4(inst. length) to the new program counter.
    • NPC <-- PC + 4 ;
  • Instruction Decode
    • Once the Instruction Register is loaded with the instruction, decoding of the that instruction along with operand fetching is done. Depending upon the instruction format (R, I or J), opcode along with the function-code fields are used to decode the instruction.
  • Execute
    • Depending upon the type of instruction(arithmetic, data transfer and control), the execution is carried out.
      • Arithmetic instructions(Add,Sub) are executed as follows: The operands are sent to the ALU with the appropriate control signal for performing the arithmetic operation. The control signals for the ALU and the MUX used to choose the second operand are derived by the control unit using the opcode and function code fields of the instruction in IR.
      • Data Instructions(Load, Store): here, only computing the effective address of the memory location is done in the EX phase.
      • Control Instructions : is branching by PC relative address): Here, the branch target address is calculated by adding the offset (given in the offset field of the instruction, loaded and sign extended in the Decode phase in the immediate register, to the N Program Counter.
      • Further the Cond register is set based on the condition specified in the instruction.
      • For unconditional branch instructions (Jump) the target address is specified as a constant in the instruction.
• RTL
  • Register Transfer Level (RTL) is a method of describing the operation of a synchronous digital circuit. The circuit's behaviour is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals.
  • RTL specifications give meaning of the instructions - how and why it happens?
  • The class slides describe RTL descriptions Load, store, Add, beq instructions pictorially.