Make sure you have done the following:
- Each Problems X has its own folder.
- Everything required to run problem X should be in X's folder.
- Every verilog file must contain exactly 1 module, which must have the same name as the file. Run name-convention-check script on the directory.
- There must also not be any illegal verilog commands.
- For HW2-HW6 and for the project demos, turn in all verilog files including the testbench files.
- Note: include the provided *_hier.v file (Without any modifications)
- Note: include a *_hier_bench.v file which instantiates *_hier.v
- Run vcheck on all you design files (exclude testbench files *_hier.v and *_hier_bench.v) and turn in .vcheck.out files.