Tools FAQ

1.  Can I use CAE machines for the homework?

No. You may not. At first this may seem to be ok, but when project starts and other homeworks come up, the inconsistencies between the CS and CAE machine will become too complicated to handle. In spite of this note, if you insist on using the CAE machines, you are welcome to, but will get no tool support from me or the TA.

2.  How to access CS machines remotely?

Read this

3.  I get a font error with ssh -X

See the student wiki entry here

4.  What combination of PRE and CLR do I use to make DFF work in mentor?

Set both to 1(Vcc).

5.  I need to connect a 4 bit wide bus to 16 bit bus. How do I do this without using 16 wires?

Instead of using the wires one can rip it using a bus ripper. There is an option rip in gen_lib to do this.

To connect individual lines of an 16 bit wide bus we need 16x1 ripper.

To connect the ripper to the bus follow the steps below:

• Flip/Rotate the ripper so that the wire ends of the ripper face the wires of the circuit you want to connect them to.
• Use the Net > Add Wire choice to connect the wire ends of the ripper to the appropriate nets/pins.
• Note that each of the wire ends has a “R” near it. This is the Rule Property of the wire end and stands for the line of the bus that is connected to that wire. For example, to connect line 2 of the bus to a wire, you have to change the corresponding “R” to “2”. Since all the “R”s will have to be changed to sequential numbers you can do this in one step. Select Text > Sequence Text. Type “0” in the Beginning Index Number and “1” in the Step By text box and click OK. Click on the “R”s one after another to change them to “0,” “1,” “2” and so on until you have done all the “R”s.
• Connect the bundle (thick) end of the ripper to the bus using the usual Net > Add Bus menu choice. Note that you do not have to perform any special actions here.

6.  How do I show a simulation and Mentor tools running on my screen to the TA (or another person) to troubleshoot a problem?

Use x11vnc which will export an existing display using vnc. Say you are logged in on emperor01.cs.wisc.edu, and you have the tools running and you are stuck at a problem you want to show the TA. At the shell prompt, type:

prompt % /u/k/a/karu/local/bin/x11vnc -display :0

1. Go find a TA (or Prof Sankaralingam) or email to see if they are available.
2. Walk to their office.
3. They can connect to your session, by executing on their prompt (or in Windows):

prompt % vncviewer emperor01.cs.wisc.edu:5900

Voila - you should see the display of emperor01.cs.wisc.edu exported as a vnc session.

7.  I'm getting expired license using vsim. What do I do?

If you are having license issues starting vsim, please type the following command:

setenv MGLS_LICENSE_FILE /s/mentor/etc/cust/mgls/mgc.licenses on your csh shell and hit "vsim".

8.  Should an unaligned memory access cause the processor to die immediately, or should it turn the memory access into a halt instruction in the memory stage and exit more "gracefully"?

You do NOT need to implement any graceful degradation behavior here. Just OR together all your err signals and propagate up to the top-level, which will cause the simulation to abruptly die without preserving any clean semantics about which instruction retired last etc. This is OK.

For these tests, you will most likely get a fail message because the output from verilog simulation and wiscalculator will not match.

9.  Can stage 3.3 on integrating the four-bank memory be skipped from the suggested stages?

Yes - this is a suggested design flow only. If your stalling memory works, you can skip this recommended stage 3.3 and directly integrate your mem_system_hier developed for homework 5 into your processor.

10.  What should the CPI be for our final processor be?

a) It varies from program to program b) I expect you to write a small set of programs to demonstrate ideal CPI and also possibly really bad CPI.

On the provided set of tests you will notice the CPI varies considerably.