Site Administration

• View
• Edit
• History
• Print
• Backlinks

• HomePage
  • Syllabus
  • Texts and References
• Course calendar
• Contact Info
  • Piazza, Mailing list
  • Pronunciation guide
• Computing
  • Tools
  • Verilog cheat sheet
  • Verilog Rules
  • Simulating Verilog
  • Verilog file naming conventions
  • name-convention-check script
  • Synthesis Tutorial
  • Common synthesis errors
• Project
  • Summary
  • Project Deadlines and Grading
  • Verification and Simulation
  • Cache Design
  • Test programs
  • Test Programs FAQ
  • Microarchitecture Specification
  • ISA Specification
  • 552 Bug Hall of Fame
• Exams
• Miscellaneous
• Learn@UW
• AllRecentChanges
• All Pages

Tasks

• Logout
• Admin tasks, Version
• Status,Notes
• Scratch
• Group attr
• Group header
• svn grading
• Project grading
• Timesheet?

edit SideBar