Verilog Filename Conventions
Enforced rule for all verilog submissions
- Every verilog file must define EXACTLY one module. If you define multiple modules in a verilog file, it will be considered a violation of cs552 verilog rules.
- If a verilog file is called xor15.v, the module it contains must be named xor15
- The filename and module name must have an EXACT one-to-one match
- YOU CANNOT have a file called 15xor.v and in it create a module called adder
- Run the name-convention-check script
- Any instantiation of a module must include port names along with net-names.i.e
clkrst c0(clk, rst) is NOT OK
clkrst c0(.clk(clk), .rst(rst)) is CORRECT
Recommended Hierarchy and Filenaming conventions
- For example, your top-level module will be called
foo_hier.v
- It MUST instantiate
clkrst
- Its interface (input/output ports) should be identical to what is suggested in your homework problems
- Name the module you are designing
foo in foo.v and instantiate foo inside foo_hier.v
- Name all submodule testbenches with the
_bench suffix
For Course Project
- We will follow this same convention for your project.
- Your topmost level with just the processor MUST be called proc.v. A template for this is already provided. See Project modules provided page.
- You must use the provided
proc_hier.v which will instantiate the clock generator and your processor.
- You must use the
proc_hier_bench.v testbench.