Course calendar and lecture notes

1.  Lecture Schedule

This course's text readings will cover Chapters 1 through 5, Appendix A, B, and Appendix C. The list of subsections omitted will be updated below (interested students can skim over them).

• 2.16 through 2.18
• 4.11, 4.12
• 5.13

Date	Topic	Reading	Homework assigned
3-Sep	Introduction	Ch 1
8-Sep	Performance + Benchmarks and Amdhal Law	Ch 2.1 - 2.15	HW1
10-Sep	Verilog Tutorial (slides above)	Skim Ch 2.17 and 2.18
15-Sep	Benchmarks and Amdahl Law	See slides and cheat sheet
17-Sep	Arithmetic & Logic	Ch 3 and Appendix B.1-B.6
22-Sep	MIPS ISA	Ch 3 and Appendix B.1-B.6	HW2
24-Sep	Processor (datapath)	Ch 3 and Appendix B.1-B.6
29-Sep	Processor (control path)	Ch 4.1 - 4.10
1-Oct	Processor (pipelining)	Ch 4.1 - 4.10	HW3
6-Oct	Processor (pipeline hazards)	Ch 4.1 - 4.10
8-Oct	Processor (pipeline hazards)	Ch 4.1 - 4.10
13-Oct	Processor (Superscalar)	Skim 4.11 and 4.12
15-Oct	Processor (MIPS R10000)	Ch 1.6 - 1.10	HW4
20-Oct	Modern processors
22-Oct	In class quiz
27-Oct	Cache concepts	no reading
29-Oct	Cache design	Ch 5.1-5.2
3-Nov	Cache design	Ch 5.3
5-Nov	Cache Performance	Ch 5.9
10-Nov	Virtual memory	CH 5.4-5.8	HW5
12-Nov	Main Memory	CH 5.4-5.8
17-Nov	ECC	review ch 5.8
19-Nov	IO	See ECC handout	HW6
24-Nov	No class	Ch 6.1-6.3
26-Nov	No class
1-Dec	Advanced Arithmetic	Ch 6.4-6.5
3-Dec	Parallel processors/shared memory	no reading
8-Dec	No class	no reading
10-Dec	No class	no reading
15-Dec	Cache Demo

2.  Lecture powerpoint slides

Lecture notes can be downloaded from a UW-madison computer (wisc.edu domain). If you trying to access from a machine off campus, use the common course login and password.

Lecture notes

Course organization and logistics

ISA

Arithmetic 1, Arithmetic 2

Performance

3.  Verilog Tutorial Slides, 01/28

• Code from verilog demo: 4 bit register (To extract: tar -xvf demo_4bit_reg.tar)
• Code from verilog demo: fsm (combinational logic implemented using a case statement) (To extract: tar -xvf demo_fsm_case.tar)
• Code from verilog demo: fsm (combinational logic implemented using assign statement and bitwise operators) (To extract: tar -xvf demo_fsm_assign.tar)

4.  Example of well written verilog code

dyser_stage.v - this is code from a design from my research group. Notice a few things in that well written example code.

• Parameters have been separated out into a separate file called dyser_config.v
• Clean separation of the sequential elements and logic
• Well written case statements
• And some syntactic things: each input, output, wire, and reg is declared on a separate line
• The module itself is simple and small. Hence easy to design, implement and verify. To build complex design, hierarchy is the key.

5.  Verilog cheat sheet - 02/10

Verilog cheat sheet pdf, Verilog cheat sheet word doc version if you want to edit,

6.  Other handouts and reference

• MIPS ISA Manual relevant pages
• RAID handout
• Error correction codes 1
• Error correction codes 2
• Booth algorithm handout prepared by Prof. Wood and Tony Nowatzki