Electronic submission instructions

Assignments Handin Instructions

For this semester we will use Canvas.

• Login to Canvas, locate the page for CS552.
• Click on "Assignments" tab, locate the corresponding assignment.
• Submit the file(s) according to instructions below.

Homework 1

1. Make a folder for each problem (hw1_1, hw1_2, and hw1_3).
2. Each folder should contain all the Verilog files for that problem. You don't have to turn in your testbench.
3. Name and signals for the top-level module should be:
   • Problem1: quadmux4_1( InA, InB, InC, InD, S, Out);
   • Problem2: fulladder16( A, B, SUM, CO);
   • Problem3: seqdec_XX(InA, Clk, Reset, Out) where XX is the sequence in hex that your module will detect (85, 97...).
4. Tar these 3 folders to hw1.tar [example: tar cvf hw1.tar hw1_1 hw1_2 hw1_3]
5. Submit only the hw1.tar file to Canvas.

Homework 2

1. Make sure you have two folders for the first two problems (hw2_1 and hw2_2).
2. Each folder must contain all the Verilog files for that problem. You may need to have copies of some files in each directory.
3. Tar these 2 folders to hw2.tar [example: tar cvf hw2.tar hw2_1 hw2_2]
4. Submit only the hw2.tar file to Canvas.

Homework 3

1. Make sure you have three folders for the first three problems (hw3_1, hw3_2, and hw3_3).
2. Each folder must contain all the Verilog files for the respective problem. You may need to have copies of some files in each directory.
   • Please double-check that you have your synthesis output folder synth/ for your bypassing rf in hw3_3/.
3. Tar these folders to hw3.tar [example: tar cvf hw3.tar hw3_1 hw3_2 hw3_3]
4. Submit only the hw3.tar file to Canvas.

Homework 4

1. Make sure you have three folders for the first three problems (hw4_1, hw4_2, and hw4_3).
   • Problem 1 folder must contain all the Verilog files for this problem.
   • Problem 2 folder must contain a folder synth/, which contains synthesis outputs for the FIFO.
   • Problem 3 folder directly contains a bunch of .asm files.
2. Tar all three folders into hw4.tar [example: tar cvf hw4.tar hw4_1 hw4_2 hw4_3]
3. Submit only the hw4.tar file to Canvas.

Homework 5

1. Make sure you have two folders for the first two problems (hw5_1 and hw5_2).
2. Tar these folders to hw5.tar [example: tar cvf hw5.tar hw5_1 hw5_2]
3. Submit only the hw5.tar file to Canvas.

Project Demo #1

1. Submit a single demo1.tar to Canvas, containing the following directories [example: tar cvf demo1.tar verilog summary]
   • verilog/: containing all Verilog files. Please copy over ALL necessary files, your processor should be able to compile and run with files from this directory alone.
   • summary/: containing the two summary log files (for unit and random tests).

Project Demo #2

1. Submit a single demo2.tar to Canvas, containing the following directories [example: tar cvf demo2.tar verilog verification]
   • verilog/: containing all Verilog files. Please copy over ALL necessary files, your processor should be able to compile and run with files from this directory alone.
   • verification/:
     • verification/mytests/: assembly (.s) files, additional tests that you have written.
     • verification/summary/: containing the two summary log files (for unit and random tests).
     • verification/instruction_timeline.pdf: the timeline you have created for the retiring instructions of perf-test-dep-ldst.asm.

Project Cache Demo

1. A state diagram of your cache controller is due a week before the cache demo.
   • Please also include your diagram in your final submission, e.g., cache_control_fsm.pdf. Put it at the same level as your cache_xxx/ folders.
2. For each version of the cache:
   • xxx_cache/verilog/: please include ALL Verilog files required to run your design.
   • xxx_cache/verification/: put the trace files named *.addr used to verify each version of the cache in the respective verification directory.
3. Tar the cache directories into cache_demo.tar [example: tar cvf cache_demo.tar assoc_cache direct_mapped_cache cache_control_fsm.pdf]
4. Submit a single cache_demo.tar file to Canvas.

Project Demo #3

1. Submit a single demo2.tar to Canvas, containing the following directories [example: tar cvf demo3.tar verilog verification]
   • verilog/: containing all Verilog files. Please copy over ALL necessary files, your processor should be able to compile and run with files from this directory alone.
   • verification/:
     • verification/mytests/: assembly (.s) files, additional tests that you have written.
     • verification/summary/: containing the two summary log files (for unit and random tests).