WISC-SP13 Microarchitecture Specification

WISC-SP13 Microarchitecture Specification

The RISC-V architecture that you will design for the final project shares many resemblances with the MIPS R2000 described in the textbook.

1.  Registers

There are thirty-two user registers, R₀-R₃₁. Like the MIPS R2000, R₀ is always zero. The program counter is separate from the user register file.

2.  Memory System

The RISC-V processor you will be implementing is a Harvard architecture, meaning instructions and data are located in different physical memories. It is word-addressable, word aligned* (where a word is 32 bits long), and big-endian. The final version of the RISC-V processor will include a multi-cycle memory and level-1 cache. However, initial versions of the machine will contain a single cycle memory. See the project deadlines for more details.

The RISC-V processor cache replacement policy is deterministic. See the cache module description for an outline of the algorithm you must use.

NOTE: For demo1 and demo2, you will work with a simplified memory model which supports un-aligned accesses

3.  Pipeline

The final version of the RISC-V processor contains a five stage pipeline identical to the MIPS R2000. The stages are:

1. Instruction Fetch (IF)
2. Instruction Decode/Register Fetch (ID)
3. Execute/Address Calculation (EX)
4. Memory Access (MEM)
5. Write Back (WB)

See Figure 6.17 on page 395 of the text for a good starting point.

4.  Optimizations

Your goal in optimizations is to reduce the CPI of the processor or the total cycles taken to execute a program. While the primary concern of the RISC-V processor is correct functionality, the architecture must still have a reasonable clock period. Therefore, you may not have more than one of the following in series during any stage:

• register file
• memory or cache
• 32-bit full adder
• barrel shifter

You may implement any type of optimization to reduce the CPI. The required optimizations are:

• There are two register forwarding paths in the RISC-V processor; one within the ID stage and between the beginning of MEM and the beginning of EX.
• All branches should be predicted not-taken. This means that the pipeline should continue to execute sequentially until the branch resolves, and then squash instructions after the branch if the branch was actually taken.