1. Usage
A simple simulator and debugger for the RISC-V ISA is provided via the makefile. You can step one instruction at a time to determine how the individual steps in your program affect the state of the machine.
One way to use this program for verification is to compare the state of registers in the writeback stage with the registers printed by this simulator.
You can run this simulator by invoking the following command at a unix prompt while in the /wiscv/tb directory:
make all PROG=program name MODE=nodut
Normal usage:
With this usage, the simulator will run the program and print a step by step listing of the instructions executed and what registers they write to etc. A file called REF.Trace will be created in a generated folder in the /wiscv/tb directory (or REF.pTrace if MODE is set to pipe).
Note: You can set the name of this generated folder by modifying the RUN_DIR.