wsrun.pl detailed usage instructions

Command-line Verilog Simulation Script

1.  Summary

This page describes how to verify verilog designs for your homework, but NOT the project. To verify/simulate your project, please refer to the project testing page, which details how to use the project makefile.

Instead of using Modelsim's builtin GUI for compilation and simulation you can use a simulation script called wsrun.pl to simulate your verilog design. This script can be used only if your verification is done using a verilog test bench.

• Add the following to your path variable: /u/k/a/karu/public/html/courses/cs552/fall2020/handouts/bins
• Identify the verilog files that you want to test, lets call them foo0.v, foo1.v, and foo2.v.
• Call your testbench foo_bench.v
• Your testbench must be written so that it will stop automatically after running for some cycles by calling $finish .
• The script will simulate your testbench and track the waveform output in a file called dump.vcd and dump.wlf. The text output of your testbench will be written to a file called transcript.
• You must instantiate the clkrst.v module in your design if you want to use this script. If you are testing pure combinational logic, simply instantiate the clkrst module in your testbench as a dummy module.
• If you use this script, you can simply edit your verilog using your favorite editor, and compile and simulate using the script, using Modelsim only as a waveform viewer.

2.  Syntax for running the script.

At the unix prompt:

prompt% wsrun.pl <name of your testbench module> <testbench file name> <list of verilog files> 

All the verilog files that your design uses must be specified on the command line. For our example, let's assume the module in the testbench is called foo_bench. Then you should execute:

prompt% wsrun.pl foo_bench foo_bench.v foo0.v foo1.v foo2.v

Note: foo_bench is specified once, and foo_bench.v is specified once. The first argument specifies the module name, the second specifies the verilog filename.

If you used the rf_bench.v from homework 3 as the testbench for example, you would issue the command:

prompt% wsrun.pl rf_bench rf_bench.v clkrst.v dff.v rf.v rf_bench.v rf_hier.v

Convert the $stop to $finish in the testbench to get this script to work with that testbench. You will then see output that looks like the following:

Compiling the following files: clkrst.v dff.v rf.v rf_bench.v rf_hier.v 
Top module: rf_bench
** Warning: (vlib-34) Library already exists at "__work".
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module clkrst
-- Compiling module dff
-- Compiling module rf
-- Compiling module rf_bench
-- Compiling module rf_hier

Top level modules:
        dff
        rf_bench
Reading /afs/cs.wisc.edu/s/mentor-2004/common/modeltech-5.8b/tcl/vsim/pref.tcl 

# 5.8b

# vsim -lib __work -c rf_bench 
# //  ModelSim SE 5.8b Jan 01 2004 Linux 2.6.9-55.0.12.EL
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2004
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# Loading __work.rf_bench
# Loading __work.rf_hier
# Loading __work.clkrst
# Loading __work.rf
VSIM 1> run -all

*** Your testbench simulation starts here ****

# ** Note: $finish    : rf_bench.v(100)
#    Time: 100010 ns  Iteration: 0  Instance: /rf_bench
Verilog simulation successful
Created a dump file dump.wlf. Open in vsim

You can now view a waveform of the simulation by issuing the following on the command-line:

prompt% vsim -view dataset=dump.wlf

You can now view all waveforms of all the signals in your design. The waveforms are saved to a file called dump.vcd and dump.wlf. In Model-sim, you will see a tab showing dataset. Click on the Edit menu and choose Wave. You can drag and drop modules into the waveform window to look at different signals as before.

If you make any changes to any of the verilog files, simply reissue the wsrun.pl command again:

prompt% wsrun.pl foo_bench foo_bench.v foo0.v foo1.v foo2.v

And re-open vsim.

You can specify wildcards like *.v to compile all the .v files.

3.  Additional flags

3.1  -wave

Will automatically start vsim with the waveform viewer after simulating your design.

3.2  -prog

Assemble the assembly file and run it on the processor.

3.3  -list

Example list file which contains one assembly file on each line:

/u/k/a/karu/courses/cs552/spring2017/handouts/testprograms/public/inst_tests/andn_0.asm
/u/k/a/karu/courses/cs552/spring2017/handouts/testprograms/public/inst_tests/andn_1.asm
/u/k/a/karu/courses/cs552/spring2017/handouts/testprograms/public/inst_tests/andn_2.asm
/u/k/a/karu/courses/cs552/spring2017/handouts/testprograms/public/inst_tests/andn_3.asm
/u/k/a/karu/courses/cs552/spring2017/handouts/testprograms/public/inst_tests/andn_4.asm

Run the programs one after another on the processor. Results are written to a file called summary.log.

3.4  -pipe

This option should be used for simulating a pipelined processor (For demo2 onwards).

3.5  -addr

This option is similar to -prog. It is used to specify an address trace to be used for HW5's mem_system_perfbench testbench. This option does not make sense for any other testbench.

3.6  -brief

Show less output on screen, record to wsrun.log